Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)

A new technical paper titled “Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage” was published by researchers at Nanyang Technological University, Cornell University, Altera, University of Waterloo and University of Toronto. Abstract “Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices. For instance, FPGAs can efficiently implement arbitrar…